Regen v0.95 + Debuggers - 模擬器

http://gendev.spritesmind.net/forum/viewtopic.php?t=510

Here you go. Some things are still broken so read the included "Notes.txt".

BIG FAT NOTE:
It is slow.
There is NO difference in term of emulation between the release 0.95 and this
one. I′ve deliberately not fixed the bugs because I didn′t wanted people to
use this because its more updated and then bitch about its speed.

If its too slow for you, you can request a much faster version which is
powered by my own 68k core. That is even more faster than the release build
by quite a bit.


Notes:


Introduction
============

This is the debug build of Regen meaning the various debuggers
are enabled in it which are disabled in the release build.
This will be very slow from the release build.

Although, I have a very fast debug build as well based on a previous
version of Regen and containing my own 68k core which was written
in optimized x86 assembly. So if this is too slow for you, you can
request that from me. My email is "aamir dot m at live dot com"

dot = .
at = @

Differences from release Regen 0.95
===================================

* Nothing, except that the debuggers are enabled.

Notes
=====

* In 68k debugger, double click on a disassembly line
to add it in as a PC breakpoint.

* 68k debugger will automatically trigger when 68k encounter
any illegal read/write.

* VRAM breakpoints won′t work due some technical reasons.

* DMA length register (VDP Reg #20) will not display correctly.

* Channel dumping from YM2612 debugger won′t work.

* Layout of VDP debugger just sucks. Help/ideas are welcomed.

My thanks goes out to Yakovlev Victor, KanedaFr and blargg.

Additions, bugs, feature requests etc... are welcomed.

Enjoy,

AamirM

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