Makaron T11/2 - 模擬器

http://dknute.livejournal.com/


The idea was to have FPGA handle the ATA interface, including DMA burst
transfers, while external MCU will run part of Makaron GD code and take care
of all the high-level stuff. 2GB Secure Digital card will provide necessary
GD data.
I realized that EP2C20 can easily host both the interface and a soft-core
NIOS II CPU with all the supporting logic for onboard memory chips. Now this
is neat, I can actually run the NIOS faster than my ARM7 and it has more
memory too (I mean, just the SDRAM is 8MB vs 64kB on-chip SRAM on ARM). The
only problem is I don't have license for that IP core so the USB programming
cable needs to be attached at all times, or the board will freeze eventually.
Both ARM and Cyclone boards have SD slots so I can change my mind anytime :)

Anyway, SPI<->SD communication works both on ARM and NIOS now (it's the same
C code, save the low-level I/O stuff). Now I need to handle FAT. There is a
free library for that but I want to write my own with a bit more buffering as
an option. Since it's read-only it shouldn't be much of a problem, it's just
that both target CPUs can only do aligned memory accesses and that needs to
be worked around for the FAT structure parsing.

VHDL code for ATA i/f is progressing, but slowly. I haven't done any of this
before - I doubt programming GAL devices counts :)

--